A vertical SiC power MOSFET is expected to be a device that will have a higher breakdown voltage, and be driven with a greater amount of current, than a vertical Si power device. Hereinafter, the structure of a conventional vertical SiC power MOSFET will be described with reference to FIG. 7, which schematically illustrates a cross section of such a conventional MOSFET in one direction (i.e., x direction in this case). It should be noted that the SiC power MOSFET also has the same structure in the direction coming out of the paper of FIG. 7 (i.e., in the y direction). And a number of unit cells, each having the structure surrounded with the one-dot chains, are arranged two-dimensionally in the x and y directions.
Each unit cell U includes a semiconductor substrate 102 of SiC (which will be sometimes referred to herein as an “SiC substrate”) and a n-type drift layer 103, which is arranged on the SiC substrate 102. A p-type well 104a has been defined in the drift layer 103 so as to spread inward from the surface 103s. Inside the well 104a, further defined are an n-type source region 105 and a p-type contact region 104b, which make ohmic contact with a source electrode 106 arranged on the surface 103s of the drift layer 103. A gate insulating film 107a has been deposited so as to cover not only portions of the well 104a that would otherwise be exposed on the surface 103s of the drift layer 103 but also the surface region of the drift layer 103 without the well 104a. And a gate electrode 108 is arranged on the gate insulating film 107a. On the other side of the SiC substrate 102, a drain electrode 101 is arranged opposite to the drift layer 103 and makes ohmic contact with the semiconductor substrate 102.
In such a unit cell U of the vertical SiC power MOSFET, if a voltage is applied to the gate electrode 108, an inversion layer to be a channel will be produced in a region of the well 104a, which is located under the gate electrode 108 and in the vicinity of the interface with the gate insulating film 107a. As a result, as indicated by the dashed lines, the electrons that have been injected from the source electrode 106 pass through the inversion layer in the well 104a, the drift layer 103 in its thickness direction and then through the SiC substrate 102 to reach the drain electrode 101 eventually. That is why the amount of current flowing between the drain electrode 101 and the source electrode 106 can be controlled according to the voltage applied to the gate electrode 108.
As described above, the unit cell U has the same structure in the y direction that comes out of the paper. That is why when viewed perpendicularly to the surface 103s of the drift layer 103, the well 104a has a rectangular shape. FIG. 8 is a perspective view schematically illustrating the arrangement of those unit cells U in the SiC power MOSFET 100. In FIG. 8, adjacent unit cells U are illustrated as if they were amply spaced from each other in order to allow the reader to see the cells more easily. Also, in FIG. 8, only the respective wells 104a of the unit cells U are shown and the flow of electrons is indicated by the dotted arrows.
As already described with reference to FIG. 7, in each unit cell U of the SiC power MOSFET 100, the electrons will move from the surface 103s of the drift layer 103 in the thickness direction of the SiC substrate 102 in the vicinity of the boundary with the adjacent unit cells U. That is why in the vertical SiC power MOSFET 100 as a whole, the electrons will move between the wells 104a in the thickness direction of the drift layer 103 and the SiC substrate 102. This “vertical” MOSFET is called as such because the source electrode 106 and the drain electrode 101 are spaced apart from each other in the thickness direction of the drift layer 103 and the SiC substrate 102 and because electrons, which are one type of carriers, move in that thickness direction.
In each unit cell U of the vertical SiC power MOSFET 100, the channel is produced around the outer periphery of the rectangular well 104a. That is why on the surface 103s of the drift layer 103, the sum of the lengths of the four sides that define the well 104a becomes the gate width. In the vertical SiC power MOSFET 100 with such a structure, the smaller the unit cell U, the longer the total gate width will be.
As shown in FIG. 9, if each side of the unit cell U1 has a length W, then the total gate width will be 4W. On the other hand, supposing each unit cell U2 has a length of W/2 each side, four unit cells U2 can be formed within the area of one unit cell U1. And as each unit cell U2 has a gate width of 2W, the total gate width will be 8W. That is why by reducing the size of the unit cells, the amount of current flowing per unit area, i.e., the current density, can be increased.
For that reason, people have attempted to make as small a unit cell as possible in the vertical SiC power MOSFET. However, as the source electrode 105 and the contact region 104b should be defined within the well 104a as shown in FIG. 7, the well 104a cannot be reduced too indefinitely to define those regions reasonably accurately. That is why it is now an important problem to solve in the field of vertical SiC power MOSFETs how in the world to shorten the interval L between the wells 104a. 
On the other hand, to drive the vertical SiC power MOSFET with as large an amount of current as possible, it is no less important to reduce the ON-state resistance. Generally speaking, in the vertical SiC power MOSFET, its ON-state resistance is calculated as the sum of source contact resistance, source sheet resistance, channel resistance, JFET resistance, drift resistance, substrate resistance and drain contact resistance. Among these various kinds of resistance, the key point is to reduce the channel resistance and the JFET resistance effectively.
As used herein, the “channel resistance” refers to the resistance of the channel to be produced under the gate insulating film 107a. According to conventional SiC-MOSFET related technologies, until just recently, the channel mobility has been low and the channel resistance has been high due to the property of the SiC material itself and owing to some difficulties with its manufacturing process. Nevertheless, as technologies for forming an oxide film have been tremendously developed these past years, it is now possible to achieve a channel mobility of approximately 30-60 cm2/Vs even on a (0001) plane of 4H—SiC. Thus, the present inventors confirmed via experiments that if the channel length was set to be 1 μm or less in a SiC power MOSFET with a unit cell size of 10 μm or less, the channel resistance could be reduced to the range of approximately 1.5 to 2.0 mΩcm2.
On the other hand, the “JFET resistance” refers to the resistance of the JFET region 111 that is interposed between two adjacent wells 104a of the drift layer 103, which provides passage for electrons that move from the source to the drain as shown in FIG. 7. As there is a pn junction between the p-type well 104a and the n-type drift layer 103, a depletion layer 110 is formed there, thus narrowing the current path and eventually increasing the resistance of the JFET region 111.
If the drift layer 103 has a normal dopant concentration of approximately 5×1015 cm−3, then the depletion layer 110 will expand when the MOSFET is turned ON. In that case, to prevent the depletion layer 110 from pinching off the path of the electrons that are moving through the JFET region 111, the interval L should be at least equal to 3 μm. Even so, however, the JFET resistance would still be relatively high.
As a result, the unit cell U comes to have an increased size and a decreased channel density, and eventually, the SiC power MOSFET will have an increased channel resistance overall. On top of that, the source contact region will account for a much smaller percentage of the overall area, and therefore, the source contact resistance will increase, which is not beneficial, either. Consequently, it is difficult to reduce the ON-state resistance of the SiC power MOSFET effectively.
In order to overcome these problems, Patent Document No. 1 discloses a technique for minimizing the expansion of the depletion layer by increasing the carrier density in the JFET region 111 to the range of approximately 1×1016 cm−3 to 5×1017 cm−3. According to Patent Document No. 1, even if the concentration in the JFET region 111 is different from, but higher than, in any other region in the drift layer, the ON-state characteristic of the SiC power MOSFET should still be improvable.